The rapid evolution of data transfer technology in recent years has been nothing short of remarkable. As industries continue to manufacture new devices and push existing devices to their limits, the need for faster and more efficient data transfer methods has taken center stage. One of the main actors on this stage is Peripheral Component Interconnect Express (PCIe). Founded in 1992 by the Peripheral Component Interconnect Special Interest Group, PCIe is the standard used by sound cards, graphics cards, networking cards, SSDs, and other peripherals to transfer data within the devices we use.
For the last few years, PCIe 5.0 has been the gold standard—and for the majority of consumer device use cases such as laptops, game consoles, and televisions, that will remain the case. PCIe 5.0 has a transfer speed of 32 GT/s. When accounting for the encoding overhead, the effective data rate is approximately 3.94 GB/s for a single-lane (x1) connection and 63 GB/s for a 16-lane (x16) connection—more than enough for everyday devices.
Industrial-level AI/ML capabilities, on the other hand, need the faster data transfer speeds brought about with the release of the PCIe 6.0 specification, supporting up to 64 GT/s per lane—a doubling of the PCIe 5.0 data rate. The higher transfer speed is enabled by introducing PAM-4 signaling for PCIe 6.0, whereas previous generations used NRZ signaling. To accommodate for noise sensitivity in PAM-4 signaling, PCIe 6.0 also includes a low latency Forward Error Correction (FEC) protocol. In addition to FEC, it is expected that many PCIe 6.0 server designs will user retimer chips to mitigate signal integrity challenges. While retimers help manage signaling issues, they do introduce latency. As a result, the PCIe spec limits the number of retimers in a link to two.
Low latency is important, since PCIe 6.0 will also support the Compute Express Link (CXL) 3.x protocol, beginning with CXL 3.0, which will be used for attaching memory and accelerators in a way that will enable completely new server architectures. Therefore, CXL interfaces will need low latency to meet the burgeoning demands of AI/ML applications of interest to hyperscalers and other providers.
Why is CXL Important?
CXL is an interconnect technology designed to handle data access between a device's central processing unit and its peripherals. While earlier versions of CXL laid the groundwork, it's the 3.x version that is truly transformative. CXL 3.x has been designed to align seamlessly with PCIe 6.0, ensuring that data transfer between the CPU and peripherals like accelerators, memory buffers, and smart I/O (input/output) devices is as efficient as possible. This isn’t just about speed or capacity, but efficiency of movement.
To use an analogy, let’s say PCIe is a major highway that serves as a link between various cities (computer components). This highway has been around for a long time and has undergone several upgrades, with PCIe 6.0 being the latest and most efficient version. As cities (computer components) grow and evolve, they develop a need for specialized traffic routes that offer faster connections. This is where CXL enters the fray. To wrap up the analogy, CXL functions as an express lane on the PCIe highway—it’s built on the same road (PCIe infrastructure) but is designed specifically for high-priority traffic. This express lane ensures that certain data can travel even faster, leveraging the full capabilities of PCIe 6.0 without interfering or being hindered by other traffic. This makes the system as a whole more efficient.
It’s important to note that while CXL is built on the PCIe interface, they are distinct entities. PCIe is a general-purpose interface used for various types of data transfers within a computer, while CXL is specifically designed for CPU-to-device and CPU-to-memory connections in data centers. They can work independently, but CXL leverages the PCIe infrastructure for its operations, and CXL 3.x has been designed specifically with PCIe 6.0 and its full potential in mind.
The Perfect Match: PCIE 6.0 and CXL 3.x
As we’ve established, the primary drivers for the adoption of PCIe 6.0 and CXL 3.x are AI and ML applications rather than consumer-focused devices. Major tech players, including NVIDIA with their graphical processing needs, are currently bearing the torch. The combined capabilities of PCIe 6.0 and CXL 3.x offer a unique solution to the low latency I/O demands of these applications where previous PCIe iterations fell short.
For instance, generative AI technologies, such as large language models, require vast amounts of data to be processed in real time in order to be useful. The enhanced bandwidth offered by PCIe 6.0, combined with the efficient data access capabilities of CXL 3.x, ensures that these models can operate at peak efficiency, even when they’re in high demand.
As AI and ML technologies continue to evolve and become more prevalent in various industries, the demand for faster and more efficient data transfer methods will undoubtedly grow. PCIe 6.0 and CXL 3.x, with their advanced capabilities and perfect alignment, may not be leveraged in consumer-focused devices for years to come, but they are already paving the way for rapid innovation in AI/ML use cases.