What Stackup Documentation Does the Fabricator Need?
A crucial step in the stackup ownership process, creating the necessary documentation to provide the chosen fabricator with precise information will enable them to build a board that is not only built to specification, but will work right the first time and every time thereafter. For the best insight into what comprises that necessary documentation, I turned to Gerry Partida, vice president of technology at Summit Interconnect. The accompanying sidebar speaks to the documentation that Summit looks for from PCB product developers.
Sidebar: A Fabricator's Guide to Developing Proper Documentation
Summit was formed in 2016 following the acquisition of KCA Electronics and Marcel Electronics International. The goal was to create a well-capitalized custom circuit board company with advanced manufacturing capabilities, industry expertise, and a software platform that makes it easy for customers to have their PCB designs reviewed and manufactured. With additional acquisitions of five factories, the company now has a total of eight factories that total over 500,000 ft^2 of manufacturing space and more than 1250 employees. In August of 2022, Summit was named as one of the 5000 fastest growing private companies by Inc. Magazine.
Through its acquisitions, Summit offers a wide range of capabilities. Its factories support sequential lamination and HDI, provide boards of all shapes and sizes, and offer a complete portfolio of PCB products for rigid, rigid-flex, flex, ATE, semiconductor, and RF/microwave designs. Each location specializes in a unique niche of the market, allowing the company to meet a wide range of PCB needs from prototypes to production quantities and standard to advanced technologies. Summit is heavily focused on high-growth markets that require complex, high-reliability PCBs. Military aerosapce continues to be a large market sector for the company, but commercial and medical sectors are also key as a result of the additional acquisitions.
As vice president of technology at Summit Interconnect, Gerry is focused on cutting-edge HDI, high speed digital, Flex/Rigid Flex and RF microwave PCB fabrication for the company’s military and commercial customers. He has been a certified IPC trainer as well as member of the IPC-6012 and IPC-6018 review committees. As he explains, “I have been part of many IPC committees for the last 12 to 14 years. In my job, it’s important to be involved in the PCB industry, to intimately understand the certifications, and to help develop future standards.”
Gerry began his career in the PCB industry at Everett Charles Test Equipment. From there, he went to Oprotech/Orbotech. He was a member of the team that introduced several key advances to the industry, including CAM automation, net list compare, and AOI CAD reference.
As a fabricator when he receives a PCB design, he explains that at the minimum, he needs a fabrication drawing. But, he points out, “There’s a great document that people don’t know about. Peter Bergman developed it in 2010, but it is still readily applicable today. The document is IPC 2614, ‘Section Requirements for Board Fabrication Documentation’. It lays out all the things you should have on that drawing and why you should have it.”
“This document tells you the things you need to define so you can express your needs and the requirements of the product you want built. In addition to the fabrication drawing, if you have your own company specifications that are outside of IPC standards, you should have those as well. In your drawing, you should identify which IPC performance spec you are building to. There are three IPC performance specs called out: IPC 6012 for rigid boards; 6013 for flex and rigid flex boards; and 6018 for RF designs.”
He continues, “In each of these documents are the rules a finished product has to meet. If you want class 2, there are certain levels; if you want more stringent levels, you go to class 3. These need to be clearly defined in your fabrication documentation. Otherwise, it defaults to class 2. If you have things outside of these standards, then you make your own specification or you put those requirements on a drawing, a PO or a SOW. The standards have an order of precedence as to what a supplier is supposed to follow. That precedence is: the PO is the master; followed by the design as provided in drawing; the customer specification and then the industry specs such as 6012 or 6013. This is the order of precedence that is usually defined in IPC documents, but they are also defined in customer specifications as well.”
Gerry and I talked about the knowledge level of product developers when it comes to their familiarization with the basic specs. He notes, “As mature as our industry is, there is still a lot of education that is needed.” And, as mature as these documents are, both product developers and fabricators need to understand what the requirements are. At least once in their career, a design engineer should read the design specs and the performance specs. The same applies to fabricators. They should read through the specs to know what the rules are.
And, as Gerry points out, the rules do change. He explains, “We’re about to roll out IPC 6012 Rev F. There will be some changes in there that help clarify requirements and improve the ways things are defined so that everybody understands the requirements.”
In terms of things that product developers may miss in the documentation process, the type of and nature of the occurrences are all over the board. Gerry states, “As an example, on a note, somebody will say ‘minimum line and space is 4’. Is that what you designed your minimum to, or is that the minimum that I need to manufacture to? So, we will go look at the design, and if the design is 4 and 4, then we just need to clarify. We can keep going, but we need to clarify. This note means that you designed to this minimum. There’s a processing tolerance window that’s typically 20% of what you provided. In document 2614, it says you should list what you designed as a minimum conductor and space. You should have another note for what you allow for a finished conductor and space. This way, it’s clear. So, when we have the finished board, we have one note for evaluation and one note for the finished board. This is an example of something that can be all over the map. Most times, there is no note, and if there is a note, there’s only one, and you’re not sure if it’s the designed or finished allowance.”
Having been on the documentation side of the equation at Martin Marietta, I know what it’s like to have to deal with the plethora of documentation that accompanies a design. It can be overwhelming. But it’s important to note that for the jobs that are put on hold at Summit Interconnect, 70% of them are done so for documentation issues.
As Gerry explains, “The hole counts will be off, or someone will ask for impedance on a line width and that line width doesn’t exist anywhere. Then, the question becomes, ‘Do we have the wrong design? Do we have the wrong revision? Did you mean the impedance to be a different line width? Were you planning to put that impedance line on that layer, but in the end, you didn’t put it there because it’s not needed, and you didn’t take the note out?’ So, the design goes on hold and all that had to be done was to check the design and remove the note so that the design isn’t on hold. That’s where the bulk of issues arise. People don’t go back and check their work and that really needs to be done.”
Gerry adds, “There are good design organizations where they go in and check everything and the designs are like butter—they come in and they go out and we don’t have to do anything with them.”
Another way in which problems come into play is when product developers are trying to put something into their design that compromises its ability to be a highly reliable design. At this point, Gerry says, “We have to say, ‘If you need to have a high reliability design, you need to understand that you are putting things at risk. It’s not that they’re out of standard, you just broke a lot of rules and you need to understand that your design is at a lot of risk.’ We can do that. We can make engineering boards that have a lot of risk but if it’s mission critical such as for manned space flight, you shouldn’t be taking those risks.’”
The good news is that most of the problems that were associated with CAD systems in the 80s and 90s have been corrected. Gerry states, “Most of the CAD systems and design software are very mature and they don’t make a lot of mistakes.”
Sidebar: Just When You Thought it was Safe to go into the Plating Line
One of the challenges associated with the PCB industry is the assumption that there is little change to it or, if there is change, it’s of nominal impact. But, as has been noted in many articles, today’s high frequency, high data rate designs are presenting some problems we have not encountered previously. Gerry explains, “One of the things we put into the design guideline IPC 2221 is that product developers should be calling out the copper type or copper profile and most of them don’t know to do that.”
“We fabricators get better yields if we have a rough copper for resist adhesion. You get better inner layer yields. Lower profile copper is smoother, it can lift off and if it lifts off for fine features, you get opens. Thus, the yields diminish. We knew at a point in time comparing between what is called RTF (reverse treated foil) and HVLP/VLP2 that the difference in yield was like 5%. We built some boards where half the boards were RTF and half were low-profile copper and we ran out of low-profile copper because we got opens. We lost more cores on the low-profile copper and we had a higher yield with the RTF. So, now there are things that we at Summit do to promote the adhesion of the resist to the low-profile copper.”
He continues, “I recently had a phone call with one of the material suppliers. He said, ‘Gerry, the copper foil suppliers are required to meet a certain maximum roughness when they give us foil. There’s no limit on how smooth it is. So, they are supplying copper foil to the laminate suppliers that is much smoother than that which they provided years ago. The laminate suppliers were banking on the adhesion of the roughness into the laminate but now it’s a lot smoother and it’s not the same peel strength. It’s still within specification but it’s not as strong as it used to be.’”
Gerry adds, “The challenge is that everybody wants low profile copper. Instead of having a plating tank making foil with normal roughness and smoothness, they just make it all the same. The suppliers are allowed to ship anything as long as it doesn’t exceed a high roughness. So now they are making foil that’s a lot smoother. We used to get foil that had 8-11 pounds of peel strength and all you had to meet was 4 or 6 pounds. Now the peel strength is actually closer to 4 or 6 pounds. We never had sheer problems before with this product but now it’s different.”
This copper issue goes beyond peel strength and surface roughness. Gerry states, “Take a look at insertion loss. If you don’t call out a profile of copper and you have a high layer count within dielectrics, insertion will now be a really big area of concern on rough copper where low profile copper will have better performance. As you get the signal layer closer to the return plane the roughness and insertion loss start showing up more. If, as the product developer, you don’t say anything, a fabricator to get their yields up will take RTF copper and there will be a certain insertion loss. But a smart fabricator will know that if the customer is buying Tachyon 100G or Megtron 7, they’re worried about insertion loss and they want high performance. So, if there is a default, at Summit, we are only buying low profile copper for these laminate systems because it's high performance. So, what happens? If I am building my boards using HVLP copper and my competitor is building the same boards using RTF copper (because the customer is dual sourcing) our boards work better. The customer only knows that our boards are better, and they can always rely on our products in terms of yield numbers and quality.”
The Next Generation of Experts: Emerging Engineers Training Program
Like the rest of us who have been in the industry for a long time, Gerry has concerns about who will be the next knowledge bearers for PCB product development. To that end, he’s very active in the IPC Emerging Engineers Training Program.
The goal of this program involves exposing young people in the industry to as much of the industry as possible throughout the course of the three-year program. This enables them to become subject matter experts much faster than those of us who are the “old timers.” It streamlines the process of learning things which took most of us approximately three decades. In order to be enrolled in the Emerging Engineers Training Program, an engineer has to have been in the industry for less than five years. Gerry explains, “You get a subject matter expert in the PCB industry to mentor you for three years. The engineers in this program get to go into IPC training programs and workshops for three years for free. At graduation, you are an emerging engineer that has completed the program. Of the 18 graduates at APEX 2023, six of them were Summit employees when they started. Five were still Summit employees when they finished, and one is a supplier to us now. We’re very proud of the engineers who completed the program; we’re very happy we took advantage of the situation, and we will continue to do so in the future. Our industry is worried as to what companies are doing to plan for the future, and the key to addressing that is to have more and better communication, collaboration, and education within the industry.”
The Bottom Line
Based on the foregoing, it’s pretty straightforward to determine that the SI engineer must take charge of the stackup design at the beginning of the PCB design process, including the crucial design to manufacturability issues, all with a watchful eye towards product reliability. Ultimately, the onus of this ownership can no longer be placed upon the fabricators.
The challenge is that PCB stackup as a design discipline is not taught in most universities. As a result, SI engineers are often reluctant to tackle the problems associated with stackup design because they have not had much experience with them. Also, there’s the associated issue of culpability. If board failures (often caused by multiple or single-points-of-failure within high data rate and high frequency designs) are traced to the stackup process, no one associated with the development of the product wants to be the owner of those failures.
The key tasks associated with stackup “ownership” is the ability to become quickly educated regarding the many factors that influence the stackup process and to ensure that the knowledge gained during any “what if” analyses is complete, correct, and will result in an optimized PCB design. Getting up to speed on potential problems and accounting for them during the stackup phase is a daunting, if not near impossible, task. Ultimately, SI engineers should not be held accountable for this information if they don’t have the necessary knowledge and toolsets at their disposal. However, there are resources available within the industry to provide more information and education as to what constitutes a good stackup design.
The foregoing is why we at Avishtech aim to provide every board designer and engineer with the ability to specify their stackup and design for impedance and signal integrity in a simple, straightforward manner. Our two most recent products, Gauss SI and SI Pro, are both low-cost and provide a clear and easy-to-use pathway to rapidly construct PCB stackups and simulate them for impedance and loss with a few quick clicks. This goal exists asthe core of our company. Similar to what Gerry Partida at Summit is doing, a large part of our effort is to educate all of the audiences who are involved in bringing a working PCB product to the table. This is not a one-shot process, and we are committed to helping not only our customers, but the broader industry as well.
In addition to our toolsets, we also have a full-up materials and testing lab. We commit an abundance of resources to identifying those laminate characteristics that are not provided in typical material data sheets and their role in the stackup. As part of these efforts, we are assisting laminate suppliers in characterizing their materials so that their customers can best determine which laminate will be the correct one for their designs.