TE Connectivity (TE) will educate and inspire system designers at DesignCon 2022 by demonstrating an array of solutions for compute and networking systems. TE will show a variety of high-speed data communications and connectivity solutions in booth 819 at the DesignCon 2022 expo on April 6-7 in Santa Clara, California. 

In addition, on April 6 at 4 p.m. at the conference, Nathan Tracy, TE technologist, industry standards manager and OIF vice president of marketing and board member, will be a moderator at the OIF panel, “Electrical I/O Specifications: Progress on CEI 112GBPS & 224GBPS.” 

Each year, the TE team demonstrates the company’s leadership in compute and high-speed connectivity solutions at DesignCon. TE’s featured live demos will include: 

112G Quad Small Formfactor Pluggable Double Density (QSFP-DD) Over-the-Board (OTB) 

  • TE has developed a connector that extends the reach of the traditional surface mount technology faceplate connectors. The near-chip socket (NCS) connector is based on existing TE socket technology to provide a dense pin field, crosstalk isolation, and a total mated height of 5.8 mm to allow for placement as close as possible to the application specific integrated circuit (ASIC). The channel includes 2 X 300mm NCS to QSFP-DD OTB cable assembly and 1.5 m QDD direct cable copper (DAC) cable assembly with a channel loss of 37 dB BGA to BGA and driven by 112G PAM4 SerDes. TE’s QSFP-DD OTB to NCS solution demonstrates how TE can use traditional PCB materials and extend the reach of the QSFP-DD channel.  

800G QSFP-DD Active Copper Cable  

  • The 800G QSFP-DD active copper cable (ACC) demonstrates the latest in TE’s bulk cable and termination technology. A retimer embedded in the module extends the reach of copper cables while consuming less power than equivalent optical cables. ACC technology also allows fine wire gauges for short links to ease routing challenges in dense next-gen racks. This live demo shows eight lanes of 112G PAM-4 data running through TE’s ACC with a host trace and connector on each side. 

Cabled Card Electromechanical (CEM) Technology  

  • TE’s Sliver connector portfolio is the backbone of this architectural shift in the market. TE uses a standardized CEM connector interface, defined within the PCI-SIG standard, in tandem with a Sliver 4C+ host connector. This configuration enables PCIe system channels to extend their reach and performance for Gen 5.0, and soon-to-be Gen 6.0 applications. TE is simplifying design choices for our industry by increasing the configurability, modularity, and optionality of our solutions to market. The mechanical strength of both the Sliver connector interface, as well as the CEM assembly, make this solution an option for almost any PCIe based application. 

Co-Packaged Socket Technology 

  • Increases in bandwidth density and adoption of higher speed protocols is putting constraints on traditional switch and server architectures. Integrating copper or optics with the silicon can help relieve some of those constraints. TE has developed socket technologies to allow a separable interface between copper or optical modules and silicon packages for co-packaged architectures. Multiple socket contact technologies allow contact pitches down to 0.40 mm while delivering excellent signal integrity performance. 

  • The display at DesignCon will showcase functionality of a co-packaged copper link leveraging TE’s co-packaged socket technology. Also displayed is a static mockup showing TE’s uLGA socket in a 51.2T Near Package Optics (NPO) switch implementation. 

PCIe Link with CDFP Technology  

  • With an increased use of disaggregated resources comes the necessity for a low latency, high performance, high density external cabling solution that is mature with proven reliability and robustness. TE will be demonstrating the use of CDFP technology as the external PCI Express cabling link by demonstrating a PCIe Gen 5.0 channel at 32 GT/s as a live demo. Current CDFP technology enables a x16 link width within a single port, allowing 512 GT/s of bandwidth and scalable to support x8 and x4 link widths in the near future. The industry has accepted CDFP technology as an external cable solution, TE’s CDFP technology connects computing appliance resources within applications such as Artificial Intelligence/Machine Learning and NVMe-based storage applications and can be used in future applications enabled by PCI Express infrastructure (such as CXL™).     

TE’s featured static demo will include: 

DDR5 Dual Inline Memory Module (DIMM) Socket  

  • TE’s fifth generation of double data rate, DIMM (DDR5) sockets include surface mount technology and can address the higher data rates needed for today’s memory module applications. Designed in accordance with JEDEC industry standards, this socket includes 288 positions, 0.85 mm pitch. DDR5 DIMM sockets support 288-Pin SMT type. This socket is designed with short, medium, long, and narrow latch options to address different space requirements. It is also available in multiple color and plating options. The DDR5 sockets are engineered for higher data rates and can provide up to two times higher performance than DDR4 DIMM sockets. DDR5 sockets are used in communication memory applications, such as data centers, desktop PCs, mass storage, and servers.  

“As the industry continues its unstoppable march toward higher speeds and denser equipment, designs require new approaches to connectivity and thermal management,” Tracy said. “Each year at DesignCon, TE demonstrates its industry leadership in developing new technologies and products to support next-generation data center and networking equipment, and we are proud to be showcasing our latest technical advances via functioning demonstrations and displays.”