Linear Technology Corporation announces the LTC6951, a low phase noise integer-N synthesizer with an integrated VCO and an ultralow jitter clock distribution section, ideal for clocking data converters. The LTC6951 features four high performance current mode logic (CML) outputs, each equipped with an independent low noise clock divider and digital delay block to cover a wide frequency range between 1.95MHz and 2700MHz. With a total of 115fsRMS absolute jitter (SNR method), the LTC6951 delivers the low jitter clocks necessary to achieve the best SNR when clocking data converters with high input frequencies and fast output data rates.

The LTC6951 introduces three intelligent schemes to simplify output clock expansion and the creation of large clock trees employed in systems with multiple daughter cards or with a large number of data converters. Linear Technology’s proprietary EZSync output synchronization method guarantees repeatable and deterministic phase relationships between all clock divider outputs on the LTC6951 and accompanying EZSync supporting devices. The ParallelSyncmultichip parallel synchronization feature allows the outputs of multiple LTC6951 ICs to be retimed to the common reference clock. This permits reference aligned synchronization in the reference clock domain with easy-to-meet nanosecond range setup and hold time requirements. The EZ204Sync JESD204B subclass 1 compliant synchronization method builds on the previous two approaches and enables the generation of the SYSREF and DEVCLK signals essential to this JEDEC standard across multiple parallel connected LTC6951 ICs along with any other EZSync compatible clock devices.

Designing with the LTC6951 is simple using the LTC6951Wizard simulation and design tool, available for free download at The LTC6951Wizard software provides appropriate PLL settings and loop filter component values with a click of a button, and accurately predicts the individual output’s phase noise and jitter. Besides performance simulation, the LTC6951Wizard GUI features a scope plot that simulates time domain results of the LTC6951 outputs based on the clock divider, delay and synchronization settings, simplifying the design process and assisting in the circuit debugging phase.

The LTC6951 is specified over the full operating junction temperature range from -40°C to 105°C. It is available in a space-saving 5mm x 7mm, 40-lead plastic QFN package. The LTC6951 is priced at $8.75 each in 1,000-piece quantities and is available immediately from stock. Samples and demo boards may be requested by visiting or by contacting your local Linear Technology sales office.

Summary of Features: LTC6951

  • Low Noise Integer-N PLL with Integrated VCO
  • 90fsRMS Output Jitter (12kHz to 20MHz)
  • 115fsRMS Output Jitter (ADC SNR Method)
  • Noise Floor Output Jitter = 
    -165dBc/Hz at 250MHz
  • EZSync Multichip Clock Edge Synchronization
  • SYSREF Generation for JESD204B, Subclass 1
  • 1.95MHz to 2.5GHz Output Frequency (LTC6951)
  • 2.1MHz to 2.7GHz Output Frequency (LTC6951-1)
  • -229dBc/Hz Normalized In-Band Phase Noise Floor
  • -277dBc/Hz Normalized In-Band 1/f Noise
  • Five Independent, Low Noise Outputs
  • Five Independent Programmable Dividers and Delays
  • LTC6951Wizard Software Design Tool Support