
Signal Integrity Journal Webinar Series
Title: Power Integrity in Practice: IR Drop and Decoupling Capacitor Analysis with CST Studio Suite
Date: December 9, 2026
Time: 8am PT / 11am ET
Sponsored by: GoEngineer
Presented by: Clint Patton, Electromagnetic Simulations - Team Lead, GoEngineer
Abstract:
Power integrity problems tend to show up late. A board passes layout review, and then a device at the far end of a rail browns out under load, or supply noise starts causing failures that are hard to trace. More often than not, the cause is the power delivery network. Either there’s too much DC voltage drop across planes and vias, or PDN impedance isn’t low enough at the frequencies that matter.
In this webinar, Clint Patton, Team Lead for Electromagnetic Simulation at GoEngineer, covers the fundamentals of power integrity and shows how to analyze them in CST Studio Suite. The session starts with how the PDN works, what causes DC IR drop, and how plane impedance, decoupling capacitors and mounting inductance affect AC performance. Clint then takes an example board through a complete power integrity workflow, from setup to IR drop and PDN impedance results, and shows how decap analysis can guide better capacitor selection and placement.
Topics include:
This session is a good fit for PCB designers, hardware engineers and SI/PI specialists who want a practical look at finding power integrity issues before a board goes to fab.
Presenter Bio:
Clint Patton began working with advanced simulation tools while pursuing his master’s degree at the Missouri S&T EMC Laboratory. He brings over 19 years of experience in the design, simulation, and testing of electronic systems for military, space, and commercial applications. In February 2023, Clint joined GoEngineer, where he supports the CST simulation platform and partners with engineers to solve complex RF, EMI/EMC, and signal and power integrity challenges. Outside of work, he enjoys spending time with his family and being outdoors.
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