EDI CON Online
Title: A Holistic Power Integrity Approach Reduces Board Spins, Supports System Analysis and Reduces VRM Modeling Effort
Date: October 20, 2020
Time: 8am PT / 11am ET
Presented by: Steven M. Sandler, Managing Director, Picotest
I hear many recurring complaints from engineers attending my lectures. They can be summarized as:
A simple design workflow could address many of these issues, resulting in more cost-effective designs with fewer expensive board spins. The proposed workflow would also reduce the effort expended by semiconductor companies in developing simulation models. The result is a unified, end-to-end model, providing power rail noise, spectral content, EMI, dynamic transient response and power rail impedance all within a single model. This approach also allows the analog, power, digital, RF and µWave models to all be incorporated into a single system level simulation model.
Steven M. Sandler has been involved with power system engineering for more than 40 years. Steven is the founder and CEO of PICOTEST.com, a company specializing in instruments and accessories for high performance power system and distributed system testing. Steven is also the founder of AEi Systems, a company specialized in worst case circuit analysis for high reliability industries.
Steven frequently lectures and leads workshops internationally on the topics of Power Integrity and Distributed Power System Design. He is a Keysight Certified EDA expert. Steven is also a recent Winner of the Jim Williams ACE Award for Contributor of the Year (2015) and a two time Test & Measurement Test Engineer of the Year Finalist. He was the recipient of both the DesignCon 2017 and EDICON 2017 Best Paper Awards.
A frequent author, Steven's most recent book is Power Integrity using ADS, published in 2020.
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