Eric Bogatin, Signal Integrity Journal Technical Editor
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Eric Bogatin is Technical Editor at Signal Integrity Journal and the Dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an Adjunct Professor at the University of Colorado - Boulder in the ECEE Dept. Eric improves the signal to noise ratio by sorting through all of the information available and finding the best quality content to publish on

Signal Integrity

New Electroless Process Promises Finer PCB Features

May 11, 2021

The conventional PCB fabrication process for printed circuit boards is subtractive. Averatek recently introduced a new chemistry technology making semi additive circuit board fabrication more attractive for ultra fine line applications.

The Averatek Semi-Additive Process

In conventional PCB fabrication technology, copper foils are laminated to dielectric layers, patterned with photo resist and everything that is not trace is etched away. This sets the limits to how fine a line can be etched and contributes to the variable trace wall shape from many processes.

Averatek, a spinoff of Stanford Research Institute, commercialized a new chemistry they call Liquid Metal Ink (LMI™). It offers an alternative approach for ultra-fine line and high aspect ratio circuit board traces. Their secret sauce is an electroless chemistry that deposits a nearly atomically conforming catalyst layer of palladium onto most dielectric surfaces. This is in contrast to conventional catalyst layers typically using either tin or palladium colloids. Conventional colloidal catalyst layers require a thicker electroless copper seed layer to achieve full surface coverage to then be electroplated, and adhesion is not as good.

Figure 1 illustrates the differences in the conventional electroless seed layers (on the left) and the LMI process (on the right), with a cross section of an electroless plated convoluted surface (inset). The palladium catalyst layer is compatible with not just electroless copper but also gold, silver, palladium, and platinum.

Figure 1. LMI creates an atomically uniform electroless metal layer on the surface of the dielectric. Conventional electroless plating can deposit thin, uniform metal layers on top of the initial seed layer which can be further grown with electroplating.

After coating and imaging with photoresist, this seed layer can be pattern plated to a desired thickness with the plated copper taking on the shape of the photoresist walls. The electroless layer can be much thinner than conventional electroless plating because the catalyst layer coverage is so dense. This means that after plating, the entire board can be flash etched without needing an etch mask. Figure 2 shows the pattern plating process to grow thicker, uniform, fine lines.

Figure 2. The fully additive Averatek process for fabricating thicker, uniform and fine lines.

The end result of this new process is straight walled, high aspect ratio, fine line copper traces which can be added to many dielectric surfaces with good adhesion. Figure 3 shows a cross section of copper traces roughly 11 µm wide by 15 µm thick.  By using the LMI enabled process, trace width and spacing as well as the aspect ratio are limited almost entirely by photolithographic capabilities. In contrast, the standard subtractive processes are limited by the ability to control etching and thus do not take full advantage of the latest advances in photolithography.

Figure 3. An example of 11 µm wide copper traces on a filled resin substrate using the LMI seed layer and pattern plated to 17 µm tall before and after flash etching.

Killer Apps

The obvious advantage of a thin, conformal electroless layer is the ability to fabricate high aspect ratio, fine lines. These features have the highest value in high pin count single chip BGAs and multi-chip modules which require fine lines from the C4 pads of the die routed through the power and ground planes and high-density signal paths and micro vias.

The LMI chemistry is an alternative to fabricate fine line, HDI layers. Where conventional fine line etching may be limited to 50 u to 25 µm line widths, the new process can achieve 12.5 µm lines and even finer, and still be compatible with conventional fab technology.

“Ultra-high-speed applications may benefit from this technology, as well,” Haris Basit, CEO of Averatek says. “The combination of very smooth copper surface and good adhesion to many low loss substrates are an attractive combination for 28 Gbps and above.” The ability to create high aspect ratio, closely coupled differential pairs may open up a new design space.

Additional characteristics of the process allow the fabrication of 3D waveguide structures or high efficiency phased array antenna patterns embedded in PCBs or on curved surfaces.

The capability of fabricating gold traces directly to liquid crystal polymer (LCP) and other biologically inert surfaces make this technology biocompatible for sensors and circuits directly implanted or in contact with living tissue. Neural probes, stimulators and glucose monitors are just a few of the bio-active applications.  Figure 3 shows an example of 24 micron wide gold traces on an polyimide film used as a direct neural interface.