As data center systems evolve to support increasingly demanding artificial intelligence (AI) and machine-learning (ML) workloads, maintaining signal integrity at 224 Gbps PAM4 has become a major architectural challenge. One of the primary limitations is insertion loss in conventional PCB traces, which increasingly constrains performance as data rates rise. This paper explores a co-packaged interconnect approach that addresses this limitation by placing the high-speed separable interface directly on the package substrate.
