Ultra-low-impedance power distribution network (PDN) structures are difficult to correlate because the impedance of the device under test (DUT) can be comparable to artifacts introduced by probe coupling, probe landing, reference-plane placement, and electromagnetic solver configuration settings. This article shows some possible full-wave 3D simulation workflows for the IEEE TC-EDMS Benchmark Problem V, a four-via test case on 1 mm pitch in which the vias are shorted together on the L2 plane.
