To keep up with the rapid advances in high-speed interfaces, you need to be able to run accurate, full-bus simulations in hours, instead of days. By converting models from transistor to power-aware IBIS behavioral, Cadence® Sigrity™ Transistor-to-Behavioral Model Conversion (T2B™) can help you meet ever-shorter deadlines by avoiding time-consuming transistor-level simulation and inaccurate non-power-aware IBIS model simulation.
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Samtec’s flyover QSFP28 cable assembly (FQSFP Series) achieves 28 Gbps performance and is backward compatible with all QSFP assemblies. This direct attach system, with press-fit tails that provide low speed signals and power to the PCB, allows drivers to be remotely located for design flexibility and greater control over thermal cooling.
Passive Plus Inc. has the 01005BB104 broadband 100 nF multilayer ceramic capacitors. The 01005BB104 – the industry’s smallest 100nF broadband part characterized for RF performance -- has a case measuring (mils) 16 x 8 x 8, and offers resonant-free RF coupling/DC blocking from 16 KHz (lower 3-dB frequency) to beyond 65 GHz with < 1 dB insertion loss and < -15 dB return loss on suitable substrates. The 01005BB104 is rated at a DC working voltage (WVDC) of 4.0 and is available in a nickel-tin termination.
Cadence® Sigrity™ XcitePI™ Extraction technology takes chip layout data in GDSII or LEF/DEF formats, and generates a comprehensive SPICE model that consists of a fully distributed PDN and I/O nets and accounts for all electromagnetic coupling effects between signals, power, and ground. 
Cadence® Sigrity™ Broadband SPICE™ technology accurately and quickly converts N-port passive-network parameters such as scattering, impedance, or admittance (S, Z, or Y) into SPICE-equivalent circuits that can be used in time-domain simulations.
The Cadence® Sigrity™ XtractIM™ tool provides a complete model extraction environment focused specifically on IC package applications. The tool generates electrical models of IC packages in IBIS or SPICE circuit netlist format. These concise parasitic models can be per pin/net RLC list, coupled matrices, or Pi/T SPICE sub-circuits.
Cadence® Sigrity™ SystemSI™ signal integrity (SI) solutions provide a comprehensive and flexible SI analysis environment for accurately assessing high-speed, chip-to-chip system designs. The solutions support industry-standard model formats and automatically connect the models. 
To ensure you get high performance at a system and component level, while at the same time saving between 15% and 50% in decoupling capacitor (decap) costs, Cadence® Sigrity™ OptimizePI™ technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre- and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your power-delivery network (PDN) needs.
Uniquely equipped to let you perform a broad range of signal- and power-integrity studies in a single step, Cadence® Sigrity™ SPEED2000™ technology is a layout-based time-domain simulation tool for IC package and/or board design. Sigrity SPEED2000 technology combines circuit and transmission-line simulations with a fast, special-purpose full-wave electromagnetic field solver.