White Papers and App Notes

cadence april

Overcoming Signal Integrity Challenges of 112G Connections

A challenge of high-frequency design is overcoming signal integrity issues, especially with 112G SerDes. For long-reach applications, signal distortion impacts clock recovery and the fidelity of the information being transferred. This white paper looks at how to handle these issues and ensure data is successfully transmitted with low BER.


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rohde february

Power Integrity eGuide from Rohde & Schwarz

This eGuide guide shows you how to make accurate power rail measurements and how impedance measurements can help to detect typical root causes of power integrity issues.

This eGuide guide shows you how to make accurate power rail measurements and how impedance measurements can help to detect typical root causes of power integrity issues.


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R&S January

Application Guide: System Level Verification and Debug of DDR3/4 Memory Designs

This application note provides an introduction to the DDR memory technology and explains common challenges, related to the specific nature of DDR data.

This application note provides an introduction to the DDR memory technology and explains common challenges, related to the specific nature of DDR data, command / address and control buses and describes the typical measurements to verify and debug DDR system designs.


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