February 28, 2017

Sponsored by: Anritsu


Editors Choice

Get it Right the Second Time
By Eric Bogatin

We all strive to, “Get it right the first time,” in our designs, and focus on skills, techniques and tools to help us achieve this. But we should also pay attention to the skills, techniques and tools to “Get it right the second time.”

A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness
By Bert Simonovich

Analysis done in this paper supports the theory that surface roughness profile decreases the separation between the reference plane(s) and conductor, thereby increasing the e-field strength, resulting in additional capacitance, which accounts for increased Dkeff and phase delay.


PAM4 Demands Accurate S-parameters
By Anritsu

  • NRZ and PAM4 Bandwidth Demands at High Data Rates
  • The Importance of Accurate S-parameters
  • Modeling and Simulation of SERDES, Interconnects, and Circuits
  • PAM4 Analysis Requires VNA Measurements


Product Design Flow Challenges
By Janine Love

An interview with Patrick Carrier of Mentor Graphics about what’s next for high-speed DDRx and SERDES designs, with a special focus on power integrity.


My Visit to the EMI Test Lab - Part of the Fun of Science
By Eric Bogatin

Recently, I had the chance to visit with Dennis King at his EMI Test Lab in Longmont, Colorado. While Dennis has been doing EMI testing for more than 30 years, he set up his independent test lab in 2004.



Learn About Channel Operating Margin Calculation, Measurement and Evolution
By Anrtisu

This white paper covers how Channel Operating Margin (COM) evolved from channel requirements at lower data rates and how it spans a multi-dimensional space of design variables, a design space.



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