PCI-SIG®, the organization responsible for the widely adopted PCI Express® (PCIe®) standard, announced the official release of the PCIe 6.0 specification, reaching 64 GT/s.
PCI Express technology has served as the de facto interconnect of choice for nearly two decades. The PCIe 6.0 specification doubles the bandwidth and power efficiency of the PCIe 5.0 specification (32 GT/s), while providing low latency, and reduced bandwidth overhead.
“PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification,” said Al Yanes, PCI-SIG Chairperson, and President. “PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backward compatibility with all previous generations of PCIe technology.”
“With the PCI Express SSD market forecasted to grow at a CAGR of 40 percent to over 800 exabytes by 2025, PCI-SIG continues to meet the future needs of storage applications,” said Greg Wong, Founder, and Principal Analyst, Forward Insights. “With the storage industry transitioning to PCIe 4.0 technology and on the cusp of introducing PCIe 5.0 technology, companies will begin adopting PCIe 6.0 technology in their roadmaps to future-proof their products and take advantage of the high bandwidth and low latency that PCI Express technology offers.”
“There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI,” said Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms, and Technologies Group, IDC. “Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance intensive computing use cases.”
PCIe 6.0 Specification Features
- 64 GT/s raw data rate and up to 256 GB/s via x16 configuration
- Pulse Amplitude Modulation with four levels (PAM4) signaling and leverages existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and enables more than double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backward compatibility with all previous generations of PCIe technology