The MIPI Alliance announced a major update to its MIPI M-PHY physical layer interface for connecting the latest generation of flash memory-based storage and other high data rate applications in advanced 5G smartphones, wearables, PCs, industrial IoT, and automobiles. Version 5.0 of the M-PHY interface adds a fifth gear—"High Speed Gear 5" (HS-G5) at 23.32 Gigabits per second (Gbps)—enabling engineers to double the potential data rate per lane compared with the previous specification. M-PHY v5.0 also responds to a range of other ecosystem requirements for connecting flash memory storage, such as ongoing improvement of the JEDEC Universal Flash Storage (UFS) standard.
MIPI M-PHY is a versatile physical layer targeting applications with a particular need for high data rates, low pin counts, lane scalability, and power efficiency. Key applications include connecting flash memory storage, cameras, and RF subsystems, as well as providing chip-to-chip inter-processor communications (IPC). For JEDEC UFS, M-PHY serves as the physical layer for MIPI UniPro, and together both specifications have been incorporated into multiple versions of UFS over the last decade.
MIPI M-PHY v5.0 is designed to support the forthcoming MIPI UniPro v2.0 and JEDEC UFS releases. In addition to doubling the data rate to a maximum of 23.32 Gbps per lane to satisfy the storage ecosystem’s growing data rate requirements, v5.0 introduces several of the latest capabilities intended to optimize the M-PHY interface:
- Data rates have been optimized for target applications, simplifying Phased Lock Loop (PLL) implementation and eliminating design complexity.
- High speed startup reduces latency, for example, when accessing flash memory on power up.
- Eye monitoring visualizes signal health, enhancing debug functionality.
- Latest attributes for equalization and other electrical updates to HS-G5 improve the suitability of M-PHY for ultra-high data rate applications.
Also, the latest version of the specification streamlines M-PHY, making several legacy features optional and further improving latency performance, boosting power efficiency, and making implementation smoother and faster. M-PHY v5.0 is backward compatible through v4.1 of the specification, and an updated conformance test suite for v5.0 is scheduled to be completed in 2022.
“The significant data rate and flexibility updates delivered in MIPI M-PHY v5.0 are the product of real-world feedback from the large base of implementers in a broad ecosystem," said Joel Huloux, chairman of MIPI Alliance. "Many of the enhancements in v5.0 come from our close relationship with the JEDEC UFS community, and such cross-industry collaboration is key to fueling and aligning innovation to better serve the global flash memory storage market.”
MIPI M-PHY v5.0 is available to MIPI Alliance members and can be downloaded from the member portal on the MIPI Alliance website. For more information, a brief MIPI Bytes video provides an overview of M-PHY and highlights its features.