Signal Integrity Journal Webinar Series

Title: From Fixing Today’s PCIe Channels to Preparing for Tomorrow’s Designs

Date: October 14, 2025

Time: 8am PT / 11am ET

Sponsored by: Keysight Technologies

Presented by: Tim Wang Lee, Ph.D., Signal Integrity Application Scientist, Keysight

Abstract:
Tackle the evolving challenges of PCIe standards with practical, solution-driven approaches. Whether you are just starting to work with the PCIe standard or have worked with the standard for a while, this session will provide signal integrity knowledge you can apply to your PCIe design workflows. Discover how to accelerate PCIe design cycles and achieve standard compliance early.

In this engaging session, attendees will explore the end-to-end channel modeling of a PCIe Gen 3 channel—starting with an underperforming design and systematically resolving SI issues. The session will highlight the journey from fixing signal integrity problems to validating the improved channel for next-generation PCIe standards (PCIe Gen 7), ensuring scalability and future readiness. Key topics include analyzing channels with input/output buffer information specification (IBIS) models, applying equalization, and leveraging standard-specific simulation and design compliance.

Whether you are refining existing designs or preparing for the next evolution of PCIe, this session equips you with actionable insights and tools to reduce re-spins by addressing key SI issues early in the design phase.

Key Takeaways:

• Gain an understanding of the PCIe end-to-end link.
• Interpret and identify practical PCIe signal integrity issues.
• Explore practical PCIe analysis through demos and practical examples.

Presenter Bio:
Chun-ting "Tim" Wang Lee, Ph.D., a Signal Integrity Application Scientist at Keysight Technologies, brings clarity to the complexities of high-speed design. With a Ph.D. from the University of Colorado at Boulder, his expertise spans from understanding how circuit board fabrication affects simulation-to-measurement correlation to pushing the limits of interconnect performance. He has characterized advanced modulation schemes such as PAM4 and ENRZ and explored channel stress testing methodologies to reveal real-world system limits. Recognized as one of DesignCon’s 40-Under-40, Tim is known for presentations that make challenging signal integrity concepts approachable and actionable. In this session, he will share insights that help engineers anticipate problems earlier, validate designs with confidence, and prepare for the next generation of high-speed systems.

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