SI/PI Simulation and Measurement Correlation Forum
Title: KEYNOTE: Addressing the 50 GHz Interconnect Design Conundrum in the Era of IEEE-P370 and 400G/800G Ethernet
Date: June 16, 2022
Time: 10:00am PDT / 1:00pm EDT
Presented by: Al Neves, Chief Technologist Officer, Wild River Technology LLC
The focus of this presentation is a systematic method of benchmarking EDA performance and insuring consistent simulation to measurement results.
There has been an accelerating convergence of tightened signal integrity requirements in the last few years. Higher signaling rates with very fast rise times (less than 12psec) with multiple levels (PAM4 and PAM6) have created a requirement for much lower return loss over extended frequencies, lower resonance and most importantly less crosstalk. New signal integrity metrics such as IEEE P370 help to define, in a general case, what “good” signal quality actually is, creating much more defined system design and test fixture performance targets.
Now, everything matters. Material properties, back drill stub lengths, and connector models are just some of the details that we will investigate as having an impact on simulation to measurement correlation.
Al Neves has 30 years of experience in design and application development of semiconductor products, capital equipment design focused on jitter and signal integrity analysis For the last 13 years he has been successfully involved with numerous business developments and startup activity. Al is involved with the signal integrity community as a consultant, high-speed system-level design manager and engineer. Recent technical accomplishments include development of platforms and methods to improve 3D electromagnetic correspondence to measure-based methods, including advancing time and frequency domain calibration methods.
Al focuses on measure-based model development, package characterization, high-speed board design, low jitter design, analysis, and training. He earned a BS in Applied Mathematics at the University of Massachusetts.
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