Anritsu Co., a DesignCon 2017 Diamond Sponsor, will present testing solutions and technical sessions to aid engineers more efficiently develop next-generation chips, boards and systems used in emerging applications, including IoT/M2M and 5G, at DesignCon, beginning January 31 in Santa Clara, CA. Signal integrity solutions featuring the award-winning Signal Quality Analyzer (SQA) MP1800A BERT, as well as the VectorStar® and ShockLine™ vector network analyzers (VNAs) will be on display in the Anritsu booth (#633) throughout the show.

Among the demonstrations will be a 56G/112 NRZ and PAM4 accurate jitter tolerance test system featuring the MP1800A with the G0374A 64 Gbaud PAM4 DAC and MP1825B 4-tap emphasis that satisfies the high accuracy and margin requirements of communications standards such as OIF, IEEE, and InfiniBand. For high-speed serial bus verification, the MP1800A will be integrated with the MP1825B and Vector Signal Generator MG3710A to conduct jitter tolerance tests on PCIe and 100GE interfaces.

The MP1800A will also be configured with the ShockLine Economy Vector Network Analyzer (VNA) MS46524B, along with Granite River Labs calibration and receiver test software to create an automated, simple, and efficient method to test Thunderbolt 3 Receiver CTS. To support the latest USB3.1 Gen2 SuperSpeed+, 10 Gbit/s receiver test standards, Anritsu will show the MP1800A with its new USB3.1 Receiver Test Adapter G0373A and dedicated high-speed serial data test software.

Also in the Anritsu booth will be the VectorStar VNA series in multiple configurations. One station will include a 70 GHz 4-port signal integrity solution and another will be a 4-port 70 kHz-110 GHz broadband VNA solution for on-wafer device characterization.

Technical Sessions

During DesignCon 2017Anritsu will host technical sessions featuring industry experts. The presentations will help engineers have greater confidence in their designs, as well as improve their test processes for faster time-to-market and lower cost-of-test:

  • Wednesday, February 1, Ballroom F – De-embedding Sensitivities, Symmetry and Differential Pair Coupling.
  • Thursday, February 2, Great America 2 Ballroom – 100G AOC/Q-SFP Test Solution (100GE, IBTA, CEI); Signal Integrity VNA Applications; High Speed Serial Bus Receiver Test Solution Toward 400G (IEEE802.3 and CEI); 56G PAM4 Bit Error Rate Test Solution.

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