EDI CON Online
Title: Ground Stitching and Copper Balancing for High Performance Si Evaluation Kits
Date: August 11, 2021
Time: 8:00am PT / 11:00am ET
Sponsored by: Samtec, Inc.
Presented by: Ted Ballou, Sr. SI Engineer, Samtec, Inc.
High-performance I/O interfaces offer small design margin for physical channel impairments such as routing impedance discontinuities and crosstalk. Mitigation techniques commonly deployed in single-purpose test/evaluation boards include thieving pads (copper balance and etch control) and stitching vias (crosstalk reduction and optimal return path). For critical high-speed nets, best practices combine these as “stitched thieving” in a parade-route configuration along the routing net. This approach is not trivial, and it becomes more challenging as designs complexity increases such as in multi-layer PCBs with BGA breakouts. In this workshop, Ted Ballou details strategies for managing layout challenges and addressing practical design constraints. Additionally, he will provide an apples-to-apples comparison of measured results with “before” and “after” PCB design iterations.
Ted Ballou is a Sr. SI Engineer at Samtec. He helps develop high speed PCB designs for testing and showcase Samtec high-performance interconnects for bleeding edge 56 Gbps PAM4 and 128G PAM4 data rates. Ted received his BSEE from the University of South Carolina.
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