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ELECTRONIC SYSTEMS SI/PI FORUM: FastPI using Standard PI Models to Expedite Platform PDN Design Optimization and Sign-off

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When

4/22/21 3:00 pm to 4/22/21 4:00 pm EST

Event Description

Electronic Systems SI/PI Forum

Title: FastPI using Standard PI Models to Expedite Platform PDN Design Optimization and Sign-off

Date: April 22, 2021

Time: 12:00pm PT / 3:00pm ET

Presented by: Kinger Cai, Platform Electrical Architect, Intel Corp

Abstract:
PCB design cycles are being accelerated with the FastPI streamlined platform power distribution network (PDN) design architecture, which provides distributed computing on private or public clouds upon a standard power integrity model (SPIM) that includes scalable unified PI target (UPIT) and compact voltage regulator model (CVRM) models.  With automated design optimization, review and signoff can be expedited to address multi-layer ceramic capacitor (MLCC) shortages and deviated power delivery networks (PDNs) in the designs of Intel customer TTM Technologies. Cost, performance, stackup, and physical dimension tradoffs are enabled with a Cadence design and analysis framework featuring Cadence® Allegro® and Sigrity™ technology upon FastPI with Intel SPIM and CVRM products.

Presenter Bio:
Kinger Cai is currently leading platform electrical architecture and design for both next generation CPU and discrete GPU facilitating I+I platform strategy in Client Computing Group in Intel Corp. Over the last 20 years, Kinger led developing several generations of client, media and mobile platforms. Kinger acquired Ph. D from Shanghai Jiao Tong university in 2001 and MBA degree from W.P Carey business school of ASU in 2008. Kinger published over 30 papers, and 14 patents with 6 granted in the US.

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