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ELECTRONIC SYSTEMS SI/PI FORUM: Sigrity 2021: 10X Performance for Next-Gen SI/PI


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4/22/21 4:00 pm to 5:00 pm EST

Event Description

Electronic Systems SI/PI Forum

Title: Sigrity 2021: 10X Performance for Next-Gen SI/PI

Date: April 22, 2021

Time: 1:00pm PT / 4:00pm ET

Presented by: 
Ken Willis, Product Engineering Group Director, Cadence
Jared James, Principal Product Engineer, Cadence
David Choe, Sr Product Engineering Manager, Cadence

Cadence® Sigrity™ 2021, the latest signal integrity (SI)/power integrity (PI) software release, includes faster engines, distributed computing, and a new user interface.  In addition, a new methodology for performing PI across multiple fabrics is now available. This presentation will introduce how the new Sigrity X-Technology distributed computing architecture is meeting the demands of SI/PI engineers across the 5G communications, automotive, hyperscale computing, and aerospace and defense industries.

Presenter's Bio:
Ken Willis is a Product Engineering Group Director focusing on system-level analysis solutions at Cadence Design Systems. He has over 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity.

Jared James is a Principal Product Engineer for Cadence Design Systems, focusing on serial link and power integrity analysis.  During his 19 years at Cadence, he has held various roles, starting as an analog/mixed signal circuit designer, focused on peak amps, samplers, serializers/deserializers and top-level mixed signal verification.  As a test engineer, he assisted with the startup of a SERDES verification lab, focusing on the characterization of PCIe IP.  This role was followed by a product engineering position supporting multiple SERDES IP with Tier 1 level customers.  He is currently the product engineer for the SystemSI serial link tool, the IBIS model generation tool T2B, and the system level power analysis tool SystemPI.  

David Choe is a Product Engineering Manager at Cadence.  He has nearly 20 years experience in analysis and modeling of high speed signal integrity, power integrity, and related electromagnetics solvers.  David has previously worked as a design engineer at Qualcomm and Qlogic, and an applications engineer at Ansys.

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