Electronic Systems SI/PI Forum
Title: DDR Crosstalk Problems Where You Least Expect Them
Date: April 22, 2021
Time: 11:00am PT / 2:00pm ET
Presented by: Jayaprakash Balachandran, Technical Lead, Cisco and Hannah Bian, Signal Integrity Engineer, Cisco
The lighting fast speeds of double-data-rate 5 (DDR5) data, require many signal integrity (SI) engineers to invest significant analysis time ensuring that data signals will meet the bit error rate (BER) and mask requirements associated with the Joint Electron Device Engineering Council (JEDEC) data bus specification. This talk will show that while the data bus gets all the glory, there are other parts of DDR design and analysis that also deserve attention. Join this presentation to see how Cisco engineers spend part of their DDR analysis time and were able to uncover a problem before the prototype stage, thereby avoiding a costly respin of a PCB.
Jayaprakash Balachandran (JP) is with Unified Compute Server (UCS) Group at Cisco Systems Inc. JP has over 16 years of experience in high-speed design and has a PhD from KUL/IMEC Belgium. He has many peer reviewed publications and leading PoC workstream in OCP/ODSA.
Hannah Bian got MSEE from Southeast University China, major in RF IC design. She is with Cisco as a Signal Integrity Engineer working on UCS server designs since 2014. She covers high speed serial IO and DDR3/4/5 channel modeling and analysis. Other professional interests include exploring new SI/PI analysis flows and methodologies to accelerate the product development cycle.
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