Find Events

or

DDR Memory System Design Verification and Debug

Registration

Register For This Event

When

10/22/20 11:00 am to 10/22/20 12:00 pm EST

Event Description

Rohde & Schwarz Webcast - Hosted By Signal Integrity Journal

Title:  DDR Memory System Design Verification and Debug

Date:  October 22, 2020

Time:  8am PT/ 11am ET

Presented By: Hermann Ruckerbauer, Owner of EKH – EyeKnowHow and Johannes Ganzert, Application Engineer-Oscilloscopes, Rohde & Schwarz

Sponsored by:  Rohde & Schwarz 

Abstract:

In this webinar, we will be talking about the best practices of doing the DDR memory system design verification and debugging with an oscilloscope. Design and verification engineers will be learning the importance of ensuring a stable operation and of reducing the risk of failure after any change over the product’s lifetime. Both require a solid characterization of the memory interface. 

We will be discussing test and tool requirements such as bandwidth, trigger and probing, which help with identifying jitter, timing and noise issues. With the help of the R&S®RTP high-performance oscilloscope, we will showcase practical measurement examples.

Presenter's Bio:

Hermann Ruckerbauer, Owner of EKH – EyeKnowHow, has over twenty years of experience in high-speed measurement and simulation, especially on DRAM-related interfaces. EyeKnowHow helps the industry by offering consulting, simulation, measurements and training for all kind of high-speed serial interfaces. After receiving his bachelor’s degree in microsystems technology from the Regensburg University of Applied Sciences, he was doing design analysis and application testing for several memory generations at Siemens/Infineon. His latest activity, before founding his own company, was the definition of the DDR4 signaling standard within JEDEC for Qimonda. With the background of DRAM internal functionally, system application requirements and high-speed signaling, he is supporting any kind of high-speed interface implementations (e.g. for 10 Gigabit Ethernet, PCIe, SATA, USB and others) with a focus on memory standards. He holds many patents and was awarded by Infineon in 2005 in the category “Outstanding Single Patent” for the patent on the “Temperature-dependent self refresh” in DDR Memory devices.

Johannes Ganzert is a senior applications engineer for oscilloscopes at Rohde & Schwarz in Munich, Germany. After graduation at the Technical University of Munich, he joined Rohde & Schwarz as a development engineer for digital hardware and software. Over time, Johannes Ganzert collected a vast experience in RF and digital applications, particularly high-speed digital design and serial buses. He is an active participant in several standardization consortia like OPEN Alliance and USB-IF.

Please note by registering for this webinar:
The details of your profile may be used by Signal Integrity Journal™ to contact you by email.

Your contact information will be shared with the sponsoring company, Rohde & Schwarz GmbH & Co.KG and the Rohde & Schwarz entity or subsidiary company mentioned in the imprint of www.rohde-schwarz.com, and you may be contacted by them directly via email or phone for marketing or advertising purposes subject to their statement of privacy.