EDI CON Online

Title: Update your SI/PI Design and Analysis Methodology for DDR and GDDR Memory Interfaces  

Date: October 20, 2020

Time: 12:30pm PT / 3:30pm ET

Sponsored by: Cadence

Presented by: Dr. Frank Zavosh, Senior Principal Product Engineer

Abstract:
Memory interfaces continue to be the biggest challenge for signal and power integrity teams. Simultaneous switching of single-ended signals at the speeds of serial links take this design challenge to a new level over the well-behaved differential pairs of peripheral component interconnect express (PCI Express). With voltage swings below one volt for the low-power versions of these interfaces, there is no longer any margin for power ripple. Design teams need a robust and proven methodology to address these challenges to ensure designs come up and work in the lab the first time.

Using the fifth version of the double data rate interface (DDR5) and the sixth version of the graphics double data rate interface (GDDR6) as examples, this workshop presents work that can be done before layout, during layout, and how to both accelerate and minimize the number of post-route re-spins due to powerful, yet memory efficient signoff simulation tools.

Presenter Bio:

Dr. Frank Zavosh is a Cadence senior principal product engineer and has 10+ years of experience in design and development of high-speed circuits and systems, test and measurement, design flow and design methodology, and numerical modeling of high-speed design. He earned his M.S. and Ph.D. degrees in electrical engineering from Arizona State University. 

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