Title: Testing Parallel Interfaces of the Future: Transmitter and Receiver Test Methods for 28 Gbps and Beyond
Date: September 12, 2019
Time: 10:30am PT / 1:30pm ET
Sponsored by: Introspect Technology
Presented by: Dr. Mohamed Hafed, Chief Executive Officer, Introspect Technology
High-speed signaling interfaces are increasingly being used in parallel wireline applications such as processor-to-processor, processor-to-memory, and processor-to-sensor links. These links require very dense — often single-ended — routing while still operating at rates of up to 28 Gbps per pin. This workshop will detail specific test and measurement considerations for ensuring the proper characterization and screening of parallel high-data rate links. We will cover topics such as protocol-based traffic generation and receiver link margining within the context of a parallel system-oriented test methodology.
Dr. Mohamed Hafed received his B.Eng., M.Eng., and Ph.D. degrees in electrical engineering from McGill University, Montréal, Canada, in 1997, 1998, and 2003, respectively. He is the Chief Executive Officer of Introspect Technology, a leading manufacturer of innovative test and measurement products for high-speed digital applications. A test industry pioneer, he has published numerous articles on the topic of analog test and built-in test, and he was the principal inventor on several patents related to signal integrity test and measurement. He was the recipient of the prestigious Government of Canada Network of Centers of Excellence Young Innovator Award, several best paper awards at industry conferences, and the D.W. Ambridge Prize for the most outstanding Ph.D. dissertation in physical sciences and engineering at McGill University. He is interested in creating and marketing innovative test and measurement solutions for the high-speed interface industry.
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