Janine Love, SIJ Editor and Technical Program Director for EDI CON
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Janine Sullivan Love

Janine Love is the editor of Signal Integrity Journal, working closely with the editorial staff and Advisory Board to bring technical, high-value content to readers in digital, video, and print formats. In addition, she serves as the technical program director for EDI CON and a contributing editor to Microwave Journal.

Power Integrity

Product Design Flow Challenges

February 21, 2017

In a follow up from my discussions with Mentor Graphics while at DesignCon, I asked Patrick Carrier, Mentor Graphics product marketing manager for high-speed PCB analysis tools, what he sees trending in product design flow. We talked specifically in terms of power integrity, SERDES, and DDRx. Patrick has been working in signal and power integrity for more than 17 years, with time spent at Dell before joining Mentor Graphics. Here’s an edited version of our discussion, where he talks about the design challenges, and how his product teams have addressed them in the company’s HyperLynx product line.

Signal Integrity Journal (SIJ): What do you wish high-speed engineers knew about power integrity?Patrick Carrier, Mentor Graphics
Patrick Carrier: First, engineers need to know how important power integrity truly is to the success of their designs.  Once that hurdle has been crossed, it is important to address not just complicated issues like looking at impedance profiles and noise propagation, but also simple ones like making sure there’s enough metal to carry DC currents and making sure their capacitors are mounted properly.  A surprising topic of discussion that comes up with many customers is via-current carrying.  Since vias tend to be short compared to the x-y dimensions of the board and the power-plane dimensions, current will distribute itself to minimize the amount of plane it has to go through, which rarely results in an even distribution amongst a set of vias — it’s all about the path of least resistance.  So extra vias that an engineer may be adding might be doing almost nothing to help.  HyperLynx has a what-if “PDN Editor” built into its LineSim pre-route tool that allows for rapidly experimenting and developing intuition on issues like via currents.  Similarly, you can use the PDN Editor to look at decoupling-capacitor mounting tradeoffs (another common area of misconceptions amongst customers).  Trying to minimize the inductance of a mounted capacitor is not always an intuitive process, and knowing when to trade off things like plane separation, via separation, and mounting distance to make a decoupling capacitor maximally effective is incredibly valuable.


SIJ: How have product design flows changed as engineers become more concerned with power integrity?
Carrier: Power integrity (PI) has become a lot more mainstream than it once was, and fewer customers now just ignore power-integrity issues. Analyses of PI issues include DC voltage-drop simulation, making sure there is enough metal on the board to carry needed currents; as well as decoupling analysis, which focuses on ensuring that there is a low-impedance path between power and ground over a range of frequencies.  Most everyone understands DC-drop issues because they are fairly intuitive, so analysis of these issues can be done by a variety of customers, and by different personnel in varying roles: it is a discipline no longer restricted to specialists.  Decoupling analysis, on the other hand, has yet to proliferate as widely, mainly due to being more complicated as well as more computationally intensive.  Many customers still use guidelines from their IC and FPGA vendors, but interest has been growing, and because HyperLynx has housed decoupling simulation in a step-by-step Wizard as well as concentrated on making it run as quickly as possible, it’s becoming more mainstream.

Customers are using these analysis types to intelligently make design tradeoffs to ensure good power delivery in their PCB designs.  With DC voltage-drop simulation, this usually means using wider, thicker, and/or more numerous metal areas and traces to carry DC current across the board.  This especially means eliminating any neck-downs that cause areas of high current density, and subsequently high temperature increases.  It also requires using the right number of vias, appropriately placed, to carry currents between layers.  With decoupling analysis, design tradeoffs typically include changing the numbers of capacitors and values of capacitors used, as well as changing how the planes in the board stackup are arranged and how the capacitors are mounted to those planes.


SIJ: Do you see the issues of SI, PI, and EMC/EMI more greatly intersecting? How? How is this affecting product design flows?
Carrier: In some ways, SI, PI and EMI/EMC do intersect more and can be considered in together, simultaneously, in an analysis.  But often it still makes more sense to look at these effects separately.  Still, the intersection of SI and PI is a popular topic, and an area HyperLynx allows exploring.  The emergence of “power-aware” SI models allows for more easily looking at problems like simultaneous switching noise, which affects fast, single-ended busses like DDR3 and DDR4, and we have added that capability to the HyperLynx DDRx Wizard.  Such models allow for a more-detailed understanding of when an SI failure will occur due to an underlying PI issue. If you can get such models, they provide valuable insight. 

But at the same time, designing low-impedance power distribution networks (PDNs) can be done independently of such models and mixed SI/PI analysis.  Large SSN simulations tend to be computationally intensive and can be time-consuming to run, so they’re typically not the most efficient way to find PDN problems. 

Proper decoupling analysis should be done first, followed by the more intensive simulations (if they’re necessary).  Decoupling analysis is also useful for looking at some EMI issues: the same capacitors that provide charge to the power pins also provide high-frequency current paths between power and ground that allow signal return currents to flow unhindered.  So, frequencies where the PDN shows a high impedance also leave the board more prone to radiation at those frequencies.  It is still impractical to simulate absolutely everything together (and will be for a long time), so users will likely continue to focus on solving specific “electromagnetic” problems with targeted, focused simulations.


SIJ: As designs become more complex, is the importance of manufacturability growing in the design process? What do you see your customers challenged with here?
Carrier: Manufacturability is always a concern, mostly in how it drives cost.  There are many high-performance materials and methods available today, but they tend to be used only by customers who aren't as cost-sensitive as others or who are working with cutting-edge technology like 50-Gbps serial interfaces.  HyperLynx allows customers to evaluate the necessity for high-performance manufacturing, and to quantify its benefits.  In most cases, customers are using HyperLynx to understand how their designs can meet their performance goals using standard, lower-cost, high-volume manufacturing, like standard trace widths and spacing, traditional thru-hole vias, and standard dielectric materials.  For faster SERDES interfaces, it is sometimes necessary to use lower-loss dielectrics and specially designed vias, incorporating backdrilling or moving to blind and buried vias.  We have also seen a recent increase in the use of rigid-flex designs, for which it becomes important to model the effects of changing impedance and delay as a trace route travels through different parts of the design, encountering varying stackups and cross sections.


SIJ: What are your customers' greatest design challenges as they approach DDRx or SERDES designs? How are you addressing these?
Carrier: With DDRx, the greatest challenge is easily the complicated timing relationships that exist between signals.  Trying to validate that all of those relationships are met, through all the worst-case conditions that might occur on the bus, is quite a daunting task.  In HyperLynx we have a dedicated Wizard for simulating DDRx busses.  It walks the customer through the simulation setup, enabling analyses that include effects like unique stimuli (for example, data bit inversion in DDR4), write leveling, crosstalk, power integrity, and even the on-chip timing relationships between signals.  The output is a comprehensive report (in HTML and Excel) which details system margins and pass/fail criteria for setup and hold time  (including derating), and/or eye diagrams and system margins.

With SERDES, the challenges are numerous, but all centered around operating at higher and higher frequencies.  At these multi-Gbps data rates, highly detailed and sophisticated models of both the ICs and the PCB interconnect become absolutely crucial to getting accurate simulation results.  On the PCB side, this means integration of 3-dimensional field solvers to accurately account for irregular structures like signal vias, DC blocking capacitors, and chip breakout routing.  In HyperLynx, we streamline the process of using our full-wave electromagnetic solver by automatically detecting any areas that require 3D modeling, so that we can generate 3D models only as necessary and re-use them whenever possible.  This makes the process of PCB modeling much more efficient while still allowing for maximum accuracy.

And on the IC side, we support a variety of models, including IBIS-AMI and SPICE models, and allow for simulation of those models in a variety of different “modes”, including generating worst-case conditions in simulations that complete in a practical amount of time.  But some SERDES specifications have adopted means of verification that require no silicon models, by using a generic set of parameters to model the ICs and focusing just on the passive interconnect meeting “compliance” standards.  A great example of this is Channel Operating Margin (or “COM”), currently used by a number of Ethernet standards as a means for measuring channel compliance.  COM makes some assumptions about driver/receiver behavior and evaluates the channel by generating a single pass/fail figure of merit, which compares signal to noise, and is expressed in dB.  The HyperLynx team has done a great deal of development in this area and actually compared the differing analysis types in detail in its 2016 DesignCon Best Paper entitled: “BER- and COM-Way of Channel-Compliance Evaluation: What are the Sources of Differences?”

SIJ: You were recently at DesignCon demonstrating your HyperLynx product line, what were your potential customers most interested in? Did you notice any trends or common challenges from your conversations with the visitors to your booth?
Carrier: At DesignCon in recent years, there’s been a strongly increasing focus on high-speed SERDES signaling, as the jump to 50-Gbps interfaces introduces a number of new challenges.  And even as SERDES interfaces have become standard on a lot of PCBs, there is still a great deal of ongoing interest in how to accurately and efficiently analyze them.  From working with 3D field solvers, to choosing smartly between different kinds of analysis, to extracting channel S-parameters and judging them against standard metrics, to simulating Channel Operating Margin, customers have been very interested in tools to get their job done and make it easier.  But as always, user interest isn't limited to only the latest, sexiest, fastest technologies. There continues to be substantial interest in working with slower interfaces, trying to meet basic SI and timing requirements.  That includes basic stackup design, and meeting manufacturing and other requirements for a wide variety of interfaces (many of them present together on the same PCBs).  Multi-board systems are also of great interest, and in general being able to analyze signal and power performance for the entire system at once. We continue to evolve and improve our products for this entire gamut of needs, with the goal of delivering the most-accurate results in the fastest, most-efficient ways.