ARTICLES

Allegro Sigrity PI Base Technology

Allegro_Sigrity_PI BaseThe Cadence® Allegro® Sigrity™ PI design and analysis environment streamlines the creation of power delivery networks (PDNs) on high-speed and high-current PCB systems and IC packages. A range of capabilities enable you to explore, optimize, and resolve issues related to electrical performance at all stages of the design cycle. The solution integrates tightly with Cadence PCB and IC package layout editors.


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Sigrity PowerSI 3D EM Extraction Option

Sigrity_PowerSI_3DMCadence® Sigrity™ PowerSI® 3D EM Extraction Option is three-dimensional (3D) full-wave and quasi-static electromagnetic field (EM) solver technology tailored for IC package and PCB design’s S-parameter model extraction for power-integrity (PI) and signal-integrity (SI) analysis. The adaptive finite element mesh (FEM) refinement technology provides consistent accuracy for complicated 3D structures.


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Sigrity PowerDC Technology

Sigrity PowerDC TechnologyThe Cadence® Sigrity™ PowerDC™ environment provides fast and accurate DC analysis for IC packages and PCBs along with thermal analysis that also supports electrical and thermal co-simulation. Targeting both pre- and post-layout applications, the Sigrity PowerDC approach enables you to quickly identify IR drop, current density, and thermal issues that are among the leading field failure risks.


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Allegro Sigrity SI Base Technology

Allegro_Sigrity_SIBaseThe Cadence® Allegro® Sigrity™ signal integrity (SI) integrated high-speed design and analysis environment streamlines creation of high-speed interconnect on digital PCB systems and IC packages. A range of capabilities—from basic to advanced—enable designers and electrical engineers to explore, optimize, and resolve issues related to electrical performance at all stages of the design cycle.


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Sigrity PowerSI Technology

Sigrity_PowerSIThe Cadence® Sigrity™ PowerSI® environment provides fast and accurate full-wave electrical analysis of leading-edge IC packages and PCBs to overcome increasingly challenging design issues such as simultaneous switching noise (SSN), signal coupling, problematic decoupling capacitor implementations, and design regions that are under or over target voltage levels.


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