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HIGH SPEED DIGITAL 3D EM FORUM: Signal Integrity and Power Integrity Optimization Work Flow for Display Sub-System in Mixed-Reality Products Using 3D Em Simulation

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When

5/26/21 3:00 pm to 4:00 pm EST

Event Description

High Speed Digital 3D EM Forum

Title: Signal Integrity and Power Integrity Optimization Work Flow for Display Sub-System in Mixed-Reality Products Using 3D Em Simulation 

Date: May 26, 2021

Time: 12:00pm PT / 3:00pm ET

Presented by: Dr. Grace Yu, Director of Electrical Engineering, Product Design Engineering Group, Mixed-Reality Team, Microsoft

Abstract:
In mixed-reality products, display quality is the most important element for achieving the overall system performance target. With the requirement to meet display brightness and image quality, six channels with fast-edge laser current were included in the display. Two major SI challenges are faced in these laser channels: first, the co-packaged multiple laser channels, consisting of rigid PCBs, connectors, flex PCB and a laser module, causing high crosstalk; and second, the nonlinear input impedance of the laser module potentially causing substantial reflection without careful optimization. These effects will degrade the laser signal quality greatly and it is critical to perform optimization to achieve the best SI. Meanwhile, the power integrity has also faced big challenges due to these high di/dt laser currents. Laser currents with fast edges excite high supply ripple noise, which can damage the performance of the laser and cause high EMI. Moreover, a large amount of supply ripple noise can be coupled to the digital core of the silicon and cause various timing errors to ASICs. In this presentation, the content is divided into three parts. First, the laser SI optimization by applying accurate 3D EM models will be covered. Secondly, several mitigations will be discussed for PDN optimization from die, package, and PCB level to reduce the power noise step by step. Finally, SI and PI simulation vs measurement correlation results will be presented.

Presenter Bio:
Dr. Grace Yu obtained a PhD degree in Electromagnetics from City University of Hong Kong and has been a Post-doctoral Research Fellow at University of Illinois at Urbana-Champaign Center for Computational Electromagnetics.  Since 2001, she moved to the Bay Area as a signal integrity engineer. Since then, Dr. Yu has worked over 20 years with extensive experiences in system-level, package-level and chip-level signal integrity and power integrity design. Most of her experiences involved highly dynamic, fast-paced and startup-like environments, such as Brocade, Nvidia, Apple, Insieme Networks (startup), Cisco, and Microsoft. She has been a technical expert and leader with an outstanding track record of engineering innovation, execution, successful product delivery, and key milestone achievements.  She has stepped up as the engineering manager for over 8 years.  Since year 2017, she has been the Electrical Engineering Director leading the signal integrity, power integrity, EMC/EMI and PCB design in Microsoft.  Her team is responsible for the SI PI EMI design optimization, signoff, and validation for mixed-reality products of Microsoft.

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