Require Registration

RSS

In this blog, Steve Sandler and Benjamin Dannan demonstrate how to determine how much CMRR is needed when introducing a ground loop isolator to correct the error in a 2-port measurement. 

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

In this article, Randy White discusses variations in clock timing and how this can impact the reliability of a memory system. White highlights the importance of considering probe calibration, random jitter removal, and controlling bandwidth for accurate measurements, providing examples that demonstrate why care must be taken during probe attachment, calibration, and using a jitter/noise analysis application to evaluate jitter levels, therefore ensuring memory reliability.

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s

Serial links have focused the practice of signal integrity on managing loss and discontinuities. Each system struggles with one or the other, making it imperative to determine which issue is dominant in your system and respond appropriately. This article by Donald Telian will explain how to characterize your link to help guide your thinking and your solution.

In this installment of Practical EMC, Kenneth Wyatt discusses the most common design issues for reducing self-generated EMI and outlines several mitigation techniques that have proved successful for challenging wireless products.

As AI and ML technologies continue to evolve and become more prevalent in various industries, the demand for faster and more efficient data transfer methods will undoubtedly grow. In this guest blog, VIAVI reviews how PCIe 6.0 and CXL 3.x, with their advanced capabilities and perfect alignment, are already paving the way for rapid innovation in AI/ML use cases. 

In this article, Donald Telian explains why discontinuities do not sum the same way as loss. Telian outlines that a failing an RL mask might indicate that Tx or Rx are simply too close to a discontinuity, causing the discontinuity proximity effect. Read on to learn more about how to to distance SerDes from discontinuities.

This article is the first part of a trilogy that aims to introduce a new paradigm in the measurement of specific electromagnetic shielding materials, namely shielding materials made from woven conductive threads. These articles highlight the shortcomings of common methods in the evaluation of such materials and introduce new approach and methodology to measure them. This new paradigm emphasizes characterization of shielding materials based on magnetic field rather than electric field. The new method introduces a measurement setup and lumped element model intrinsic to the material and independent from the measurement method.

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.