eBook Library
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The material presented in these PDF documents is owned by the sponsoring company and Signal Integrity Journal™. It is presented here to be downloaded by an individual for educational purposes. It may not be downloaded from this site and reposted elsewhere.
eBooks by Content Type:
New eBooks:
SIJ 2024 Issue: The Road from 1 Gbps-NRZ to 224 Gbps-PAM4
Subscribe to download this issue of Signal Integrity Journal featuring articles from industry experts including:
- “Generative AI is in Your Future,” Eric Bogatin, Signal Integrity Journal
- “The Road from 1 Gbps-NRZ to 224 Gbps-PAM4,” Augusto (Gus) Panella, Molex
- “IEEE802.3dj Work on 200 Gbps per Lane and How Different FEC Options Affect SI,” Cathy Ye Liu, Broadcom
- “PCB Laminate Anisotropy: The Impact on Advanced Via Modeling,” Bert Simonovich, Lamsim Enterprises
- “Introducing an Upcoming IEEE Packaging Benchmark,” Istvan Novak and Gustavo Blando, Samtec; Shirin Farrahi, Kristoffer Skytte, and John Phillips, Cadence; Abe Hartman, Oracle; Ethan Koether, Amazon; and Mario Rotigni, STMicroelectronics
- “Assessing the Accuracy of EM Simulation Tools,” Aakriti Srivastava, Micron; Eric Bogatin, Melinda Piket-May, Mohammed Hadi, and Aditya Rao, Univ. of CO
- “Who Put that Inductor in My Capacitor?,” Will McCaffrey, Tyler Huddleston, Benjamin Dannan, and James Kuszewski, Northrop Grumman Mission Systems
- “Worst-Case Bit-Pattern Generator for Eye Diagram Analysis of Non-LTI High-Speed Channels,” Majid Ahadi Dolatsara, Keysight Technologies
- “DesignCon Returns to Celebrate Engineers and Innovation,” Suzanne Deffree, DesignCon
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High Speed Interconnect Solutions Guide
The importance of high-speed interconnect solutions cannot be overstated. Whether powering the backbone of global telecommunications networks, accelerating the data processing capabilities of cloud computing infrastructure, or enhancing the performance of consumer electronics, these solutions are the foundation upon which modern connectivity is built. This eBook guide covers interconnect design challenges for 224G systems and PCIe 6.0 plus the various testing techniques needed to evaluate and test these systems. The introductory article also covers some history of how we have progressed from 1 Gbps NRZ to 224 Gbps PAM4 so is a nice perspective on the evolution of interconnect technology.
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Identifying and Solving EMC/EMI Problems
The need to address EMC/EMI problems has never been more pressing. As electronic devices become smaller, faster, and more powerful, the potential for interference grows exponentially. It's no longer sufficient to simply design and build electronic systems without considering their EMC/EMI characteristics. Engineers, designers, and technicians must proactively identify and mitigate these issues to ensure that their products meet regulatory standards, perform reliably, and avoid costly setbacks. This eBook provides an understanding of the underlying principles, practical methodologies, and advanced techniques for dealing with EMC/EMI challenges. It is designed for both newcomers seeking a foundational knowledge of the subject and experienced professionals looking to deepen their expertise.
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Getting the Jitter Out - High Speed Communications Timing Technology
This eBook focuses on jitter, simply defined as any effect that causes signal threshold crossing times to deviate from their expected positions. The first article addresses the inter-relationships between jitter and other noise-generating mechanisms.
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End-to-End High-Speed Digital Design
High-speed digital links at 224 Gbps per lane, device miniaturization, and ultra-low power budgets result in sophisticated systems that are more complex to optimize signal integrity performance and reliability. Engineers require close collaboration and seamless flows from concept to simulation, emulation, and testing to keep up with technology's pace and meet shrinking time-to-market expectations.
This eBook covers how to connect design workflows to make end-to-end high-speed digital design a reality. It will discuss the challenges and trade-offs associated with optimizing design performance for technologies such as PCIe 6.0, USB4 Version 2.0, and USB-C, DDR5, and LPDDR.
