Melinda Piket-May

Electromagnetic simulation tools will almost always give a result for any problem after pressing the run button. But is the result accurate? A methodology is introduced to establish the best practices for using the Ansys 2D Extractor and HFSS tools that include recommendations for the setup conditions, balancing accuracy, and computation time. With this methodology, an error in the absolute accuracy when solving for some electrical features can be achieved to better than 0.3%.

In part three of the Ultra-Fine Line Design Guide series, previously introduced methodology is used to explore the design space for a differential pair when the return plane is far enough away that coupling to it is negligible. Read on. 

In this series, experts extend the exploration of design space to ultra-fine line features. Read on. 

With the recent introduction of the Averatek Semi-Additive Process (A-SAP) process, linewidths under 1 mil are possible using the same fabrication processing line as for traditional 4 mil wide lines. This opens up the possibility of using narrower traces in the BGA escape region than in long-path routing regions. However, using this routing architecture means the narrower traces in the BGA escape field are at a higher impedance than the wider, 50 ohm traces in the routing region. So, how long can these traces be before the impedance mismatch is a problem? The authors of this piece propose an analysis methodology to find out.

Few topics are as fundamental in signal integrity and create as much confusion as signal bandwidth. What exactly does bandwidth refer to and what features in the time domain influence bandwidth; rise time or slew rate?

The first goal in any high-speed board stack up design is to engineer interconnects with a target impedance, and the first step in this process is to use a 2D field solver to explore design space with a virtual prototype. Just how well can a field solver predict the impedance of traces on a real board? This article aims to answer this question.