Signal Integrity Journal

AI in Power and Signal Integrity Design: Revolutionary or Overhyped?

Sun, 24 Aug 2025 00:00:00 -0400

Follow along as Steve Sandler tests and evaluates the capabilities of generative AI using numerous experimental prompts related to SI/PI.

Generative Solutions vs. Discriminative Models

Sat, 07 Jun 2025 00:00:00 -0400

The future of signal integrity design is being reshaped by AI and machine learning. Traditional SPICE and IBIS models are giving way to generative AI, digital twins, and physics-informed models that offer real-time insights and future-proofing capabilities. Chris Cheng discusses why AI is no longer just data-driven—it’s becoming physics-aware, adaptable, and ready to co-pilot your next design.

Ethernet in the Age of AI

Tue, 30 Jul 2024 00:00:00 -0400

In this blog, John D'Ambrosia discusses the industry's approach to Ethernet in the age of AI, from the IEEE P802.3dj project to the efforts of the Ultra Ethernet Consortium to deliver a complete cost-effective Ethernet architecture optimized and scalable for high-performance AI. Read on to understand the role of these two complementary efforts to support AI workloads and gain insight into potential industry growth.

A New Look For S-Parameters

Tue, 12 Oct 2021 00:00:00 -0400

SIJ editorial advisory board member Yuriy Shlepnev offers a comparison of three ways to visualize the same s-parameter data, identifying how to get the most information from a plot.

Validation of Bend Models with Measurements

Wed, 22 Sep 2021 00:00:00 -0400

Bends in PCB traces look like very basic, simple structures that are easy to simulate. Technically, one can do the analysis with any electromagnetic solver with sufficiently accurate port de-embedding capabilities. The reflections from a bend in fine-line, high-speed digital interconnects are relatively small and may not even be detectable with measurement. So, who cares? Read on to find out more.

112 G for Quickest Data Transfer

Wed, 01 Sep 2021 00:00:00 -0400

Data usage is increasing every year, and the communications industry is working diligently to support the increased demand. This article discusses why we need more data, what data center physical layer architecture changes are needed to support higher data rates, and how connector manufacturers are improving designs to support higher data rate systems.

112 Gbps PAM4 Silicon and Connector Evaluation Platform

Tue, 20 Jul 2021 00:00:00 -0400

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors.

PCI Express: Is 85 Ohms Really Needed?

Tue, 05 Jan 2021 00:00:00 -0500

We want to follow this mantra of 85 ohms for PCIe, but it may not be so easy. Here’s a look at exactly what the spec says, and what we can do about it.

Does DC Block Capacitor Location Matter?

Tue, 22 Dec 2020 00:00:00 -0500

Gustavo Blando, a Samtec signal integrity architect, recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.

Channel Operating Margin: An In-Context Channel Compliance Method

Tue, 08 Dec 2020 00:00:00 -0500

Mechanical needs and power limits are at odds with what is optimal for signal integrity. Having a metric that guides us to the sufficient SI choice rather than going for the optimal SI choice ultimately saves cost and decreases time to market. Read on for the details on Brandon Gore’s technique.

Reflections on How to Become an Industry Influencer

Mon, 16 Mar 2020 00:00:00 -0400

Bert Simonovich explains why you should take your shot at becoming an industry influencer, offering tips to get started and to keep moving.

Point to Multipoint Non-Contact Interconnect Bus: Necessity Is the Mother of Invention

Tue, 17 Dec 2019 00:00:00 -0500

Bert Simonovich reminisces about the problems and innovations that led to the invention of the point to multipoint non-contact interconnect bus.

The Reality of 56/112 Gbps PAM4 Data Transmission

Tue, 03 Dec 2019 00:00:00 -0500

Routing 112 Gbps PAM4 signals through a system poses many challenges for designers. In this piece, SI expert Scott McMorrow explains what causes signal degradation and offers a path forward.

Practical Modeling of High-speed Channels Based on Data Sheet Input

Mon, 02 Oct 2017 00:00:00 -0400

As Dave Dunham from Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.

Via Stubs – Are They all Bad?

Fri, 10 Mar 2017 00:00:00 -0500

We worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”