Mechanical needs and power limits are at odds with what is optimal for signal integrity. Having a metric that guides us to the sufficient SI choice rather than going for the optimal SI choice ultimately saves cost and decreases time to market. Read on for the details on Brandon Gore’s technique.
PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.