Items Tagged with 'PAM4'

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.

In preparation for 224 Gb/s and beyond, Samtec engaged in a research project to characterize the transmission performance of emerging PCB material sets. Brandon Gore explores the current state of the art for PCBs and cables, comparing them and assessing the technology gap to fully support the insertion loss performance required for higher data rates.

Portfolio of products designed to support tech leaders, hyperscale data center, and enterprise customers to meet increasing demands of generative AI, ML, 1.6T networking, and other high-speed applications.

New software tools support faster 64 GT/s data transfer speeds using PAM4 multi-level signaling.

In this paper, the signal integrity design challenges of 224Gbps-PAM4 networking system are analyzed, and the key enablement solutions are proposed to meet the end-to-end (E2E) loss budget of ≤ 40 dB.

Recent studies indicate that the industry is nearing the precipice where plated through hole via technology has reached a limit in supporting serial links with 28 GHz Nyquist frequency requirements. At DesignCon2021, a team from the Mayo Clinic presented this paper about their work to extend the “life” of conventional PCB technology.

SIJ recently caught up with Timothy Vang, vice president of marketing and applications for Semtech’s Signal Integrity Products Group about the company’s latest product for 50Gbps PAM4 5G front haul deployments, how signal integrity and RF/wireless design overlap, and what is next for the team at Semtech.

Data usage is increasing every year, and the communications industry is working diligently to support the increased demand. This article discusses why we need more data, what data center physical layer architecture changes are needed to support higher data rates, and how connector manufacturers are improving designs to support higher data rate systems.

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. 

With the growth of 5G data traffic and AI computing, data centers need faster connectivity to meet the increasing bandwidth. High speed I/O speed beyond 112 Gb/s per lane is required. If we follow the SerDes technology revolution by doubling the data rate per lane in every 2-3 years, the next generation I/O data rate will be 224 Gb/s. In this article, Cathy Liu explores options, technical challenges, and potential solutions to achieve 224 Gb/s per lane.