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This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.
