Items Tagged with 'jitter'

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DDR5 Input Clock Jitter Tests

DDR5 Electrical and Timing Measurement Techniques

In this article, Randy White discusses variations in clock timing and how this can impact the reliability of a memory system. White highlights the importance of considering probe calibration, random jitter removal, and controlling bandwidth for accurate measurements, providing examples that demonstrate why care must be taken during probe attachment, calibration, and using a jitter/noise analysis application to evaluate jitter levels, therefore ensuring memory reliability.


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Thumbprint F3

Evaluating Oscillator Power Supply Noise Rejection: It’s the Total Jitter that Matters

Designers pushing the limits in their application can run into situations where the XO performance is inadequate for their next design due to the way it reacts to the noise and ripple in the power supply. To achieve optimal performance, they most likely will find they will need to do more than a simple datasheet evaluation to select their next XO. Read on for details on a PSNR test method to help select an optimal XO.


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