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Part 2 - Demystifying Vias in High Speed PCB Design


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8/8/18 1:00 pm to 8/8/18 2:00 pm EST

Event Description

Part 2 - Demystifying Vias in High Speed PCB Design

August 2, 2018
10am PT / 1pm ET
Sponsored by Keysight Technologies
Presented by Hee-Soo Lee, Lead Application Developer/SerDes Product Owner, Keysight Technologies

Why this webcast is important:

Selecting the right decoupling capacitors for flat target impedance improves the power integrity of a power delivery network while often decreasing cost. Modern high speed designs have both mission mode simultaneous switching noise (SSN) and state change step loads that that exceed the response time of the voltage regulator module (VRM), and are lower frequency than what the on-die and package capacitors can handle. The decoupling capacitors must fill this gap and deliver the required power in this mid-range of frequencies between the VRM and the package/die target impedance bandwidth. The decoupling capacitors must also insure stability with the voltage regulator and minimize the “bandini mountain” parallel resonance with the package inductance.

In this webinar, we will discuss a simple but very effective Z Input Impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.

Who should view this webcast:

PCB designers wanting to gain a greater knowledge of vias and how to properly characterize and model them in PCB design, and also the audience who attended: Part 1 - Demystifying Vias in High Speed PCB Design.