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Best Design Practices for Systems with PDN Noise-Sensitive Circuits

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When

4/19/18 11:00 am to 4/19/18 12:00 pm EST

Event Description

Signal Integrity Webinar Series

Title:  Best Design Practices for Systems with PDN Noise-Sensitive Circuits

Date:  April 19, 2018

Time:  8am PT/ 11am ET

Presented By:  Steve Sandler, Founder of Picotest

Sponsored by:  Rohde & Schwarz

Abstract:

Most of the power integrity focus is on high power devices, such as FPGAs and CPUs. Most power distribution networks (PDNs) also include sensitive circuits including LNAs, clocks, and PLLs, often even within the FPGAs. These sensitive circuits can be sensitive to microvolts of noise. The challenge is that over-designing the power supply adds unnecessary cost while under-designing the power supply results in suboptimal performance.

In this webinar we’ll answer these important questions, provide the essential information you need and allay your fears:

  • Are these types of circuits all sensitive?
  • How do I know how sensitive the circuit is?
  • How do I fit between over-design and under-design?
  • What about the special RF linear regulators?

Who should attend:  

Engineers that are responsible for power supply design and/or selection, power integrity engineers, signal integrity and system engineers and all engineers interested in improving power related performance.

Presenter Bio:

Steve Sandler has been involved with power system engineering for nearly 40 years. Steve is the founder of PICOTEST.com, a company specializing in power integrity solutions including measurement products, services, and training. He frequently lectures and leads workshops internationally on the topics of power, PDN, and distributed systems and is a Keysight certified expert for EDA software.

He frequently writes articles and books related to power supply and PDN performance and his latest book, Power Integrity: Measuring, Optimizing and Troubleshooting Power-Related Parameters in Electronics Systems, was published by McGraw-Hill in 2014.