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Mainstream SERDES Design and Analysis


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1/31/18 11:00 am to 12:00 pm EST

Event Description

Signal Integrity Webinar Series

Title:  Mainstream SERDES Design and Analysis

Date:  January 31, 2018

Time:  8am PT/ 11am ET

Content By:  Patrick Carrier

Sponsored by:  Mentor, A Siemens Business


So you're designing SerDes links running between 5 and 25 Gbps? What do you need to look at to make sure that your board will work the first time, and meet your performance goals? It depends on the protocol, and can involve time-domain metrics such as eye masks or frequency-domain metrics such as insertion loss. Whatever protocol you might be using, simulating your channel before boards are made will greatly increase the chances of a robust design.

What you will learn:

  • Requirements for simulating popular SerDes protocols
  • New analysis methods

Who should attend:

  • Signal integrity engineers
  • Electrical engineers
  • PCB engineers
  • Engineering managers

Presenter Bio:

Patrick Carrier worked as a Signal Integrity Engineer at Dell for 5 years before joining Mentor in September 2005. Patrick is now a technical marketing engineer specializing in analysis products, including signal and power integrity, EMC, and thermal design.