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Designing Double-Data Rate (DDRx) Memory Interfaces Right the First Time

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When

7/15/21 11:00 am to 7/15/21 12:00 pm EST

Event Description

Altair Webcast - Hosted By Signal Integrity Journal

Title: Designing Double-Data Rate (DDRx) Memory Interfaces Right the First Time

Date: July 15, 2021

Time: 8am PT / 11am ET

Presented by: Saigopal R M, Applications Engineer – Electronics, Altair

Sponsored by: Altair

Abstract:
More and more smart connected devices need high-speed DDRx memory interfaces. The design of memory circuits has always required care, but PCB layouts for DDR memory are more demanding and traditional rules-based approaches are no longer sufficient, especially for the latest DDRx memory interface standards. Learn how Altair PollEx enables the optimization of DDRx timing, transmission lines, topology, and terminations ensuring signal integrity.  

Presenter Bio:
Saigopal R M is an Application Engineer for Electronics and EDA solutions at Altair. Over the last 5 years, he has assisted several engineers in mitigating Signal Integrity, Power Integrity and EMI issues (at PCB level). Sai started his career as PCB layout engineer in 2014 and has worked on several complex designs. He has experience in analyzing and troubleshooting DDRx/LPDDRx, ATCA and 100GBE interfaces.

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