Eric Bogatin, Signal Integrity Journal Technical Editor

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Get six experts in a room together and you are likely to hear seven different opinions. Not so at the Future of Power Integrity Panel Discussion at DesignCon 2019.  The consensus of this panel of experts is that the future of power integrity will include single processor chips drawing as much as 1000 A and more. Read on for the details of this discussion!

Now that you have been working in industry for some years, you know what you regret not learning when you had the chance. This book is your second chance.  Read on for a book review of Electric Circuits, a Primer, by JC Oliver, published by Artech House, 2018.

In exploring options to demonstrate ringing from reflections in transmission lines, Professor Eric Bogatin gets a greater understanding of debouncing circuits. Read on to see where his investigations led him.

Eric Bogatin explores just how much better the sine wave is from a more expensive function generator compared to the lower cost units. He asks the question: Just how much bang do you get for your buck? Read on to see how he does it.

The third Electronic Design Innovation Conference (EDICON), was held Oct 17-18, 2018 in Santa Clara. The attendees were treated to two days of technical talks, tutorials and tradeshow with the overlapping topics of RF, SI, PI and EMI. This is a unique combination, allowing cross fertilization between these otherwise separate fields.

We usually associate problems with the power distribution network (PDN) as from excess VRM noise, or from transient current draw from the core or I/O drivers. But that’s not the only source of PDN noise. Some failures can arise from dull, boring, mundane problems at DC.

Eric Bogatin reviews a presentation by Terence Regan, and shares his thoughts on the topic of high-performance interconnect design and fabrication.

No matter how well you understand the design principles, and no matter how much experience you have in designing boards, it’s easy for some problems to slip through the cracks because you just forgot to check that feature, or your design is just too big to manually check. This is where a design rule checker comes in.

At DesignCon 2018, the IEEE P370 standards group announced the release of two important tools to assist all engineers for de-embedding. In the presentation by Jason Ellison and Heidi Barnes, “A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics”, the two new tools were announced, a board kit and a de-embedding software tool.