DC Blocking Capacitor Location, who cares?

It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pros and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.

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Sources and Compensation of Skew in Single-Ended and Differential Interconnects

VNA measurements showed that the board-to-board skew distribution of realistic board topologies/routes can be broad, and the peak measured skew was quite significant. Post processing of TDR data suggested that long routes parallel to the board edge may be particularly susceptible to skew variation due to the glass weave.
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S-parameter Renormalization, The Art of Cheating

As you know, "us", Signal and Power Integrity Engineers, are full of tricks, rules of thumb, and shortcuts. These tricks mostly help us understand something, save analysis time and, why not, make us look smarter than we really are!! In that vein, seldom have I encountered a quick and dirty trick as useful and underestimated as S-parameter renormalization.

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