40 GHz PCB Interconnect Validation: Expectations vs Reality

By Marko Marin and Yuriy Shlepnev

What does it take to design PCB interconnects with good analysis-to-measurement correlation up to 40 GHz? Is it doable with typical low-cost PCB materials and fabrication process, typical trace width, via back-drilling and the shortage of space to place the stitching vias? This paper reports lessons learned from validation projects with the goal to build a formal procedure for systematic prediction of interconnect behavior up to 40 GHz. Topics include: selection of test structures, connectors and measurement equipment, and analysis uncertainties.

Executive Q&A: Jeff Waters, president and CEO of Isola Group

Signal Integrity Journal recently caught up with Jeff Waters to check in on his progress over the last two years since he took over as president and CEO of Isola Group discussing improvements in their operations and new products.

Samtec Releases Over 100,000 New Models on SnapEDA

Samtec is releasing new digital models for over 100,000 of its products on SnapEDA, the circuit board design library. With this new collaboration, designers can now easily discover, download, and design with over 100,000 ready-to-use Samtec connector models, helping accelerate the design process.

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How to Solve Signal Integrity Problems: The Basics

By Keysight Technologies

In this video, we will show you how to use basic signal integrity (SI) analyses such as eye diagrams, S-parameters, TDR and single pulse response to solve signal integrity problems. The video links you to an example ADS workspace already set up with the essential SI simulations. Watch now.

EDI CON China 2019 Opens Call For Abstracts

EDI CON China 2019, a conference that brings together engineers working on high frequency analog and high speed digital designs, taking place April 1-3, 2019 at the China National Convention Center in Beijing, announces the Call for Abstracts for its technical sessions is open.

Upcoming Webinars

Analysis and Verification of DDR3/DDR4 Interfaces

DDR3/4 DRAM Memory is one of the last remaining parallel interfaces in current industry standards. It is expected to stay parallel (as the "dinosaur" of interface definitions) for the next generation of memory. Design and especially verification and debugging of the interface is a difficult task due to several specialties of DDR signaling, which will be covered in this webinar.

PAM4 Jitter, Noise, and BER Analysis

In this seminar techniques for analyzing the performance of PAM4 transmitters and receivers will be discussed. After a brief review of the PAM4 scheme, we dive into jitter and noise analysis of three eye diagram PAM4 signals including the key transmitter diagnostic and compliance tests. We then turn to receiver tolerance testing for both diagnostics including techniques for generating stressed PAM4 signals and measuring both the symbol and bit error ratios.

Test Vehicles for Benchmarking 3D Full-Wave Solver Performance

High-speed designers who need to design test fixtures as well as backplane designers working on 10-32Gb/s NRZ to 112G PAM-4 can benefit from adopting high-confidence design methodologies when using 3D full-wave solvers. This webinar aims to help you build better test, characterization, and backplane systems, by improving understanding and avoiding the common pitfalls. Learn more and register.

Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.